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| Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET FEATURES * 'Trench' technology * Very low on-state resistance * Fast switching * Stable off-state characteristics * High thermal cycling performance * Surface mounting package PHT6N03LT SYMBOL d QUICK REFERENCE DATA VDSS = 30 V ID = 5.9 A g s RDS(ON) 30 m (VGS = 5 V) RDS(ON) 28 m (VGS = 10 V) SOT223 DESCRIPTION GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHT6N03LT is supplied in the SOT223 surface mounting package. PINNING PIN 1 2 3 tab gate drain source drain 4 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k Tamb = 25 C; VGS = 10 V Tamb = 100 C; VGS = 10 V Tamb = 25 C MIN. - 55 MAX. 30 30 13 5.9 4.1 23.6 1.8 150 UNIT V V V A A A W C ESD LIMITING VALUE SYMBOL PARAMETER VC Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 k) MIN. MAX. 2 UNIT kV THERMAL RESISTANCES SYMBOL PARAMETER Rth j-sp Rth j-a Thermal resistance junction to solder point Thermal resistance junction to ambient CONDITIONS mounted on any pcb mounted on test pcb of fig:17 MIN. TYP. MAX. UNIT 70 15 K/W K/W January 1998 1 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET ELECTRICAL CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS V(BR)GSS VGS(TO) RDS(ON) gfs IDSS IGSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C IG = 1 mA VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C VGS = 5 V; ID = 3.2 A VGS = 10 V; ID = 3.2 A VGS = 5 V; ID = 3.2 A; Tj = 150C Forward transconductance VDS = 25 V; ID = 5.9 A Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 150C Gate source leakage current VGS = 5 V; VDS = 0 V Tj = 150C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 5.9 A; VDD = 24 V; VGS = 5 V MIN. 30 27 10 1 0.6 8 - PHT6N03LT TYP. MAX. UNIT 1.5 24 18 14 0.05 0.02 24 3 11 30 80 95 40 3.5 3.5 7.5 1050 270 140 2 2.3 30 28 51 10 500 1 10 45 130 135 55 V V V V V V m m m S A A A A nC nC nC ns ns ns ns nH nH nH pF pF pF VDD = 15 V; ID = 5.9 A; VGS = 5 V; RG = 5 Resistive load Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 5.9 A; VGS = 0 V IF = 5.9 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 25 V TYP. MAX. UNIT 0.75 100 0.4 5.9 10 1.2 A A V ns C January 1998 2 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET AVALANCHE LIMITING VALUE SYMBOL PARAMETER WDSS Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 5.9 A; VDD 15 V; VGS = 10 V; RGS = 50 ; Tamb = 25 C MIN. - PHT6N03LT MAX. 60 UNIT mJ 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 100 ID / A DS / ID 7830-30 10 RD S( ) ON =V tp = 10 us 100 us 1 DC 1 ms 10 ms 0.1 100 ms 0 20 40 60 80 100 Tamb / C 120 140 0.01 0.1 1 10 VDS / V 100 1000 Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tamb) Fig.3. Safe operating area. Tamb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Zth j-amb / (K/W) BUKX83 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% Normalised Current Derating 1E+02 D= 0.5 0.2 0.1 0.05 0.02 P D tp D= tp T 1E+01 1E+00 1E-01 0 0 20 40 60 80 100 Ambient temperature, Tamb (C) 120 140 T t 1E-02 1E-07 1E-05 1E-03 t/s 1E-01 1E+01 1E+03 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tamb); conditions: VGS 5 V Fig.4. Transient thermal impedance. Zth j-amb = f(t); parameter D = tp/T January 1998 3 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHT6N03LT 60 50 40 ID / A 10 6 BUK9830-30 5 4.5 20 gfs / S 9830-30 4 VGS / V = 30 20 10 0 3.5 10 Tj / C = 25 150 3 2.5 0 2 4 VDS / V 6 8 10 0 0 10 20 30 ID / A 40 50 60 Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS RDS(ON) / mOhm 3 3.5 9830-30 4 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V a 60 50 2 SOT223 30V Trench Normalised RDS(ON) = f(Tj) 1.5 40 30 20 10 0 VGS / V = 4.5 5 10 6 1 0.5 0 10 20 30 ID / A 40 50 60 0 -50 0 50 Tj / C 100 150 Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS ID / A Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 3.2 A; VGS = 5 V VGS(TO) / V max. BUK959-60 60 50 40 30 20 10 0 9830-30 2.5 2 Tj / C = 25 1.5 typ. 150 min. 1 0.5 0 1 2 3 VGS / V 4 5 6 0 -100 -50 0 50 Tj / C 100 150 200 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS January 1998 4 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHT6N03LT 1E-01 Sub-Threshold Conduction 60 50 IF / A 9830-30 1E-02 40 1E-03 2% typ 98% 30 Tj / C = 150 1E-04 25 20 10 0 1E-05 1E-05 0 0.5 0 0.5 1 1.5 2 2.5 3 1 VSDS / V 1.5 2 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS C / pF Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj WDSS% 10000 9528-30 120 110 100 90 80 70 60 50 40 Ciss 1000 Coss Crss 100 0.1 30 20 10 0 20 40 60 80 100 120 140 Ambient temperature, Tamb (C) 1 VDS / V 10 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz VGS / V 5 VDS / V = 6 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tamb); conditions: ID = 5.9 A 9830-30 24 + L VDS VDD 4 3 VGS 2 -ID/100 T.U.T. R 01 shunt 0 RGS 0 5 10 QG / nC 15 20 25 1 0 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 5.9 A; parameter VDS Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD ) January 1998 5 Rev 1.300 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PRINTED CIRCUIT BOARD PHT6N03LT Dimensions in mm. 36 18 60 9 4.6 4.5 10 7 15 50 Fig.17. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick). January 1998 6 Rev 1.300 |
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